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datasheet low emi, spread modula ting, clock generator ICS91730 idt? low emi, spread modulating, clock generator 1 ICS91730 rev f 061611 features/benefits ? ICS91730 is a spread spectrum clock targeted for mobile pc and lcd panel applications that generates an emi-optimized clock signal (emi peak reduction of 7-14 db on 3rd-19th harmonics) through use of spread spectrum techniques. ? ICS91730 focuses on the lower input frequency range of 14.318 to 80.00 mhz with a spread modulation of 20khz to 40khz. specifications ? supply voltages: vdd = 3.3v 0.3v ? frequency range: 14.318 mhz < fin > 80 mhz ? cyc to cyc jitter: <150ps ? output duty cycle 45-55% ? 0c to +85c operation ? 8-pin soic ? reference input pin configuration functionality block diagram clkin 18 pd # * vdd 27 sc lk gnd 36 sd ata clkout 45 ref_out/fs_in1 * 8 pin soic * internal pull-up resistor fsin_1 0 -0.8 down spread 1 -1.25 down spread 27.00mhz in --> 27.00mhz out mhz spread % default 14.318 mhz in --> 27mhz out
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 2 ICS91730 rev f 061611 pin descriptions pin # pin name pin type description 1clkin pwrin p ut for reference clock. 2vdd inpower su pp l y , nominal 3.3 v 3 gnd out ground p in . 4 clkout i/o modulated clock out p ut. un-modulated 3.3v reference clock out p ut. fre q uenc y select latch in p ut. refer to the functionalit y table. 6 sdata pwr data p in for smbus circuitr y , 5v tolerant. 7 sclk pwr clock p in of smbus circuitr y , 5v tolerant. 8pd#* pwr asynchronous active low input pin, w ith 120kohm internal pull-up resistor, used to pow er down the device. the internal clocks are disabled and the vco and the cr y stal are sto pp ed. * internal pull-up r esistor ** internal pull-down r esistor i/o ref_out/fs_in1* 5
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 3 ICS91730 rev f 061611 table 1: frequency configuration (see i2c byte0) above is the hard coded 5 bit (32 entry) rom table. fs3:0 are only accessible through i2c software programming bits (byte0 bits5:7). fs4 can also be decoded from fs_in1 latched input hardware pins. fs_in1 fs4. upon power-up the default is to use hardware selection of fs_in1 latched value. fs3 = 0, fs2 = 0, fs1 = 0, fs0 = 1 upon power-up (refer to the functionality table on page 1). to access non-default spread entries in the rom, byte0 programming should be used. in order to change the power up default of fs_in1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software selection by switching this bit to a ?1? and then program the desired percentage by changing byte0 bits 7:3. fs4 fs3 fs2 fs1 fs0 sprd typ e sprd % 00000 0.60 00001 0.80 00010 1.00 00011 1.25 00100 1.50 00101 2.00 00110 0.50 00111 1.00 01000 0.60 01001 1.00 01010 -0.80 01011ctr spd +/-0.3 01100 1.50 01101 1.75 01110 2.00 01111 2.50 10000 3.00 10001 1.25 10010 0.40 10011 0.50 10100 0.70 10101 1.00 10110 1.20 10111 1.50 11000 0.60 11001 0.80 11010 1.00 11011 1.25 11100 1.50 11101 2.00 11110 0.50 11111 1.00 down spread (-) down spread (-) 48in/48out 66in/66out down spread (-) center spd (+/-) 14in/27out down spread (-) center spd (+/-) 14in/14out 27in/27out center spd (+/-)
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 4 ICS91730 rev f 061611 general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit read address write address d5 (h) d4 (h) index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 5 ICS91730 rev f 061611 byte 0 pin # name control function 0 1 pwd bit 7 - fs0 spread/fs0 rw 1 bit 6 - fs1 spread/fs1 rw 0 bit 5 fs2 spread/fs2 rw 0 bit 4 fs3 spread/fs3 rw 0 bit 3 fs4 fs4 rw 0 bit 2 pd# tri_sate pd# tri_sate rw h i-z low 1 bit 1 spread enable spread enable rw off on 1 bit 0 hw/sw control s prea d s pec t rum c on t ro l fs 3:4 hard/software select rw hw sw 0 byte 1 pin # name control function 0 1 pwd bit 7 ref_out ref_out_enable rw d isable enable 1 bit 6 - ref_out slew r ate ref-out rw nominal fast 1 bit 5 fs-in_1 fs-in_1 readback r - - x bit 4 (reserved) (reserved) r- - 0 bit 3 clk_out slew rate c lk-out rw nominal fast 1 bit 2 clk_out clk_out_enable rw d isable enable 1 bit 1 (reserved) (reserved) r- - 1 bit 0 (reserved) (reserved) r- - 1 byte 2 pin # name control function 0 1 pwd bit 7 x- ( reserved ) -- -1 bit 6 x ( reserved ) ( reserved ) rw d isable enable 1 bit 5 x ( reserved ) ( reserved ) rw d isable enable 1 bit 4 x ( reserved ) ( reserved ) rw d isable enable 1 bit 3 x ( reserved ) ( reserved ) rw d isable enable 1 bit 2 x ( reserved ) ( reserved ) rw d isable enable 1 bit 1 x (reserved) (reserved) rw d isable enable 1 bit 0 x (reserved) (reserved) rw d isable enable 1 byte 3 pin # name control function 0 1 pwd bit 7 x ( reserved ) ( reserved ) rw - - 1 bit 6 x ( reserved ) ( reserved ) rw - - 1 bit 5 x ( reserved ) ( reserved ) rw - - 1 bit 4 x ( reserved ) ( reserved ) rw - - 1 bit 3 x ( reserved ) ( reserved ) rw - - 1 bit 2 x ( reserved ) ( reserved ) rw - - 1 bit 1 x ( reserved ) ( reserved ) rw - - 1 bit 0 x (reserved) (reserved) rw - - 1 affected pin affected pin affected pin affected pin srpead pecentage see table1 these are i2c bits only type bit control type bit control bit control type type bit control
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 6 ICS91730 rev f 061611 byte 4 pin # name control function 0 1 pwd bit 7 x (reserved) (reserved) rw -- 1 bit 6 x (reserved) (reserved) rw -- 1 bit 5 x (reserved) (reserved) rw -- 1 bit 4 x (reserved) (reserved) rw -- 1 bit 3 x (reserved) (reserved) rw -- 1 bit 2 x (reserved) (reserved) rw -- 1 bit 1 x (reserved) (reserved) rw -- 1 bi t 0 x (reserved) (reserved) rw -- 1 byte 5 pin # name control function 0 1 pwd bit 7 x ( reserved ) ( reserved ) - -- 1 bit 6 x ( reserved ) ( reserved ) - -- 1 bit 5 x (reserved) (reserved) - - - 1 bit 4 x (reserved) (reserved) - - - 1 bit 3 x (reserved) (reserved) rw -- 1 bit 2 x (reserved) (reserved) rw -- 1 bit 1 x (reserved) (reserved) rw -- 1 bit 0 x (reserved) (reserved) rw -- 1 byte 6 pin # name control function 0 1 pwd bit 7 x revision id bit 3 ( reserved ) r- - 1 bit 6 x revision id bit 2 ( reserved ) r- - 1 bit 5 x revision id bit 1 (reserved) r- - 1 bit 4 x revision id bit 0 (reserved) r- - 1 bit 3 x vendor id bit 3 (reserved) r- - 1 bit 2 x vendor id bit 2 (reserved) r- - 1 bit 1 x vendor id bit 1 (reserved) r- - 1 bit 0 x vendor id bit 0 (reserved) r- - 1 affected pin type bit control type bit control affected pin affected pin type bit control
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 7 ICS91730 rev f 061611 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ICS91730. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristics?input/ supply/common output parameters t a = 0 - 85c; supply voltage v dd = 3 .3 v +/-5% parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma powerdow n current i d d3. 3pd 15ma fin = 14.318mhz 2 27 41 ma fin = 66.67mhz 2 32 50 ma input frequency fi v dd = 3.3 v 14.318 mhz pin inductance lpin 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t tra ns to 1st crossing of target frequency 3 ms settling time 1 ts from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms delay 1 t pzh ,t pzl output enable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. input c apacitance 1 operating current i d d3.3op 2 operating current depends on both the input and output frequencies. the values shown represent the upper and lower extremes. the higher the input/output frequency, the higher the current draw . the relationship is linear.
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 8 ICS91730 rev f 061611 electrical characteristics?clkout electrical characteristics?ref t a = 0 - 85c; v dd = 3.3v +/-5%; c l = 15 pf (unless otherwise specified) parameter symbol conditions min typ max units output h igh voltage v oh 3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 rise time tr3 v ol = 0.41v, v oh = 0.86v 0.5 0.6 1 ns fall time tf3 v oh = 0.86v v ol = 0.41v 0.5 0.6 1 ns duty cycle d t3 measurement from differential wavefrom - 0.35v to +035v 45 50 55 % jitter, cycle to cycle t jcyc-cyc 1 v t = 5 0% 50 150 ps 1 guaranteed by design, not 100% tested in production. t a = 0 - 85c; v dd = 3.3v +/-5%; c l = 15 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 14.318 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 ? output h igh voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1 .0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @ min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.2 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.2 2 ns duty cycle d t1 1 v t = 1.5 v 455155% jitter t jcyc-cyc 1 v t = 1.5 v 105 300 ps 1 guaranteed by design, not 100% tested in production.
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 9 ICS91730 rev f 061611 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8 part / orde r number shipping packa ging pack age te mperature 91730amlf tubes 8-pin soic 0 to +85c 91730amlft tape and reel 8-pin soic 0 to +85c
ICS91730 low emi, spread modulat ing, clock generator idt? low emi, spread modulating, clock generator 10 ICS91730 rev f 061611 revision history issue date who description page # 06/25/04 add lead free package description to ordering information 10 06/29/04 add revision history table to datasheet. 11 05/23/05 1. revise abs max ratings. 2. updated ref electrical c haracteristics table. 3. updated lf ordering information from "lead free" to "rohs compliant". 8-10 06/04/08 updated mlf ordering info 9 06/16/11 rdw 1. added operating current specs that were inadvertantly ommitted 2. updated ordering info to latest format 3. changed c l from "10-20 pf" to 15 pf 1, 7-9 rev. c b d e f
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